1. Field of the Invention
The present invention provides a method and apparatus of transmitting data signals and control signals, and more particularly, to a method and apparatus of transmitting control signals via a reserved bit of an LVDS interface.
2. Description of the Prior Art
Liquid crystal display (LCD) devices are flat panel displays characterized by thin appearance, low radiation and low power consumption. LCD devices have gradually replaced traditional cathode ray tube (CRT) displays, and been widely applied in various electronic products such as notebook computers, personal digital assistants (PDAs), flat panel televisions, or mobile phones. An LCD device usually includes an LCD panel, a timing controller, a gate driver, and a source driver. The timing controller generates data signals corresponding to display images, together with control signals and clock signals for driving the LCD panel. The source driver generates driving signals based on the data signals, the control signals and the clock signals received from the timing controller. For displaying images correctly, various signals are transmitted from the timing controller to the source drivers via an interface. Common interfaces used in an LCD device include transistor-transistor logic (TTL) interfaces, reduced swing differential signal (RSDS) interfaces, low voltage differential signal (LVDS) interfaces, and mini low voltage differential signal (mini-LVDS) interfaces, etc.
Reference is made to FIG. 1 for a diagram of a prior art LCD application system 10. The LCD application system 10 includes a panel control device 12 and an LCD device 14. Signals are transmitted between the panel control device 12 and the LCD device 14 via an LVDS bus. The panel control device 12 generates image signals DIMAGE, a horizontal synchronization signal HS, a vertical synchronization signal VS, and a data enable signal DE, etc. The LCD device 14 includes a timing controller 16 and a display panel 18. Based on the horizontal synchronization signal HS, the vertical synchronization signal VS, and the data enable signal DE, the timing controller 16 generates a start pulse signal SP, a data load signal LD, and a polarity signal POL for operating the LCD panel 18. Based on the image signals DIMAGE, the timing controller 16 generates data signals DATA corresponding to display images of the LCD panel 18. Since an LVDS bus is used as a signal transmission interface between the panel control device 12 and the LCD device 14, an LVDS transmitter is disposed on the panel control device 12. The signals DIMAGE, HS, VS and DE are outputted via channels TX0-TX3 of the LVDS transmitter, and the clock signal is outputted via a TCLK channel of the LVDS transmitter. Similarly, an LVDS receiver is disposed on the timing controller 16. The signals DIMAGE, HS, VS and DE outputted by the LVDS transmitter are received via channels RX0-RX3 of the LVDS receiver, and the clock signal is received via a RCLK channel of the LVDS receiver.
Reference is made to FIG. 2 for a signal diagram illustrating the operation of the LCD application system 10. FIG. 2 depicts signals outputted via the channels TX0, TX1, TX2, TX3 and TCLK of the LVDS transmitter, in which eight red image data signals R0-R7, eight green image data signals G0-G7, eight blue image data signals B0-B7, the horizontal synchronization signal HS, the vertical synchronization signal VS, and the data enable signal DE are being transmitted. Within a cycle as illustrated in FIG. 2, the LVDS transmitter outputs the data signals R0-R5 and G0 via the channel TX0, outputs the data signals G1-G5 and B0-B1 via the channel TX1, outputs the data signals B2-B5, the horizontal synchronization signal HS, the vertical synchronization signal VS, and the data enable signal DE via the channel TX2, and outputs the data signals R6-R7, G6-G7 and B6-B7 via the channel TX3. In the LVDS bus specifications, the channel TX3 includes a reserved bit which is not used for signal transmission. Therefore in the prior art LCD application system 10, data outputted via the channel TX3 in a cycle is one bit less than that outputted via other channels.
Reference is made to FIG. 3 for a diagram of a prior art LCD device 30. The LCD device includes a gamma power generator 32, a timing controller 36, a display panel 38, and source drivers CD1-CDn. The timing controller 36 receives the image signals DIMAGE, the horizontal synchronization signal HS, the vertical synchronization signal VS, and the data enable signal DE provided by an external system via an LVDS receiver, and generates the start pulse signal SP, the data load signal LD, and the polarity signal POL for operating the LCD panel 38. Also, the gamma power generator 32 provides a gamma DC voltage VGAMMA and a common voltage VCOM for operating each source driver. The DC voltage VCOM is the basis for performing gamma DC voltage VGAMMA conversion in each source driver. If the gamma DC voltage VGAMMA and the common voltage VCOM deviate from the predetermined values due to device characteristic variations or system mismatches, brightness irregularities may occur when the display panel 38 display images of the same gray scale. This kind of flicking largely influences the display quality of the LCD device 30. Therefore, the LCD device 30 usually includes variable resistors for manually adjusting the value of the common voltage VCOM.
Also, an LCD device displays images having different gray scales by changing the rotations of liquid crystal modules. For human eyes, each frame appears as an independent image. When displaying consecutive frames, human eyes perceive overlapped images of two consecutive frames as a result of persistence of vision. The kind of image overlapping is more obvious when an LCD device displays motional images. Image overlapping can be reduced by increasing the response speed of the liquid crystal material, but the response speed has its upper limit. Usually a technique known as black image insertion is introduced for inserting black images between two consecutive frames and thereby providing fast pulse modulation effect similar to that provided by the CRT devices. Human brains automatically filter image flickering and generate intermediate images, which can thus reduce the visual effect of image overlapping. Since the maximum vertical synchronization frequency provided by most LCD devices is 75 Hz, the frame has to be updated every 13.3 microseconds. Therefore, when using the black image insertion technique, a black image has to be switched to a normal image within 6.66 (13.3/2) microseconds, and a normal image has to be switched to a black image within 6.66 microseconds plus a vertical blanking period. The purpose is to prevent the brightness of a normal image from being influenced by a black image, or from being overlapped by a normal image of the next frame.
As a result, a technique known as over-driving is further introduced together with the black image insertion for increasing the response speed of the liquid crystal material. An over-driving circuit is disposed on a scaler that generates display images of an LCD panel, and a black image insertion circuit is disposed on the LCD panel. If the LCD panel provides black image insertion function, a scaler capable of supporting over-driving has to be used and the manufacturing process is very complicated. Besides, although over-driving and black image insertion techniques can reduce visual effects caused by image overlapping when displaying motional images, image contrast distortions can occur when displaying static images.